Electrostatic discharge (ESD) protection of high speed devices such as the protection of switch pins that extend to switch nodes with a fast rise time requirement, encounters problems when it comes to dealing with high voltages. The high voltage requirements are typically addressed by making use of an array having multiple fingers defining the protection device, to handle the high currents. However, multiple fingers invariably increase the footprint of the device, which implies a large parasitic capacitance associated with the array. This in turn is incompatible with the fast rise time requirement of the switch node.
Furthermore, in the case of LDMOS-SCR devices it has been found that drain-source avalanche breakdown cannot be used to reliably turn on the device since the extended drain in such a device acts as a saturation resistor which disperses the turn-on voltage. Therefore snapback of the device cannot be achieved reliably. Thus, a circuit such as that shown in FIG. 1, which makes use of an LDMOS-SCR 100 to protect a switch node 102, and which relies on avalanche breakdown to turn on, does not provide for a reliable solution.
Gate turn-off (GTO) thyristors have, in the past been used to provide precise turn-on by using the gate electrode as a control electrode.
The present invention seeks to provide a solution to these problems while making use of an LDMOS-SCR device.